恩智浦 龙邱K66 KEY例程20.01.17

恩智浦 龙邱K66 KEY例程

  1. 宏定义
    优先级寄存器宽度

    #define PORT_PCR_IRQC_SHIFT                      16	//IRQC[19:16]
    #define PORT_PCR_IRQC_MASK                       0xF0000u	//1111 0000 0000 0000 0000 保留IRQC
    #define PORT_PCR_REG(base,index)                 ((base)->PCR[index])	//选择对应寄存器,指向
    #define PORT_PCR_IRQC(x)                         (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)	//IRQC赋值
    #define PORT_PCR_PE_MASK                         0x2u	//启用上拉或下拉电阻
    #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
    #define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
    #define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
    #define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
    #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */	//4位优先级宽度
    #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */	//0000 0000 0000 0111<<8 = 0000 0111 0000 0000
    #define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */	//PRIGROUP位置为SCB->AIRCR[10:8]
    #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
    #define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
    volatile uint8_t key_exti_flag = 3;
    
  2. 初始化全局变量、枚举与结构体(请自行查找文档)
    NVIC->ISER
    SCB->AIRCR
    CMSIS-Core异常定义

    typedef struct
    {
      __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
      uint32_t RESERVED0[24];
      __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
      uint32_t RSERVED1[24];
      __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
      uint32_t RESERVED2[24];
      __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
      uint32_t RESERVED3[24];
      __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
      uint32_t RESERVED4[56];
      __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
      uint32_t RESERVED5[644];
      __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
    }  NVIC_Type;
    typedef struct
    {
      __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
      __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
      __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
      __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
      __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
      __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
      __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
      __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
      __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
      __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
      __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
      __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
      __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
      __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
      __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
      __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
      __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
      __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
      __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
      uint32_t RESERVED0[5];
      __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
    } SCB_Type;
    typedef struct {
      __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
      __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
      __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
           uint8_t RESERVED_0[24];
      __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
           uint8_t RESERVED_1[28];
      __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
      __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
      __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
    } PORT_Type, *PORT_MemMapPtr;
    typedef enum exti_cfg
    {
        zero_down     = 0x08u,     //低电平触发,内部下拉
        rising_down   = 0x09u,     //上升沿触发,内部下拉
        falling_down  = 0x0Au,     //下降沿触发,内部下拉
        either_down   = 0x0Bu,     //跳变沿触发,内部下拉
        one_down      = 0x0Cu,     //高电平触发,内部下拉
    
        //用最高位标志上拉和下拉
        zero_up       = 0x88u,     //低电平触发,内部上拉
        rising_up     = 0x89u,     //上升沿触发,内部上拉
        falling_up    = 0x8Au,     //下降沿触发,内部上拉
        either_up     = 0x8Bu,     //跳变沿触发,内部上拉
        one_up        = 0x8Cu      //高电平触发,内部上拉
    } exti_cfg;
    typedef enum IRQn {
      /* Auxiliary constants */
      NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
    
      /* Core interrupts */
      NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
      HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
      MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
      BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
      UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
      SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
      DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
      PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
      SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
    
      /* Device specific interrupts */
      DMA0_DMA16_IRQn              = 0,                /**< DMA Channel 0, 16 Transfer Complete */
      DMA1_DMA17_IRQn              = 1,                /**< DMA Channel 1, 17 Transfer Complete */
      DMA2_DMA18_IRQn              = 2,                /**< DMA Channel 2, 18 Transfer Complete */
      DMA3_DMA19_IRQn              = 3,                /**< DMA Channel 3, 19 Transfer Complete */
      DMA4_DMA20_IRQn              = 4,                /**< DMA Channel 4, 20 Transfer Complete */
      DMA5_DMA21_IRQn              = 5,                /**< DMA Channel 5, 21 Transfer Complete */
      DMA6_DMA22_IRQn              = 6,                /**< DMA Channel 6, 22 Transfer Complete */
      DMA7_DMA23_IRQn              = 7,                /**< DMA Channel 7, 23 Transfer Complete */
      DMA8_DMA24_IRQn              = 8,                /**< DMA Channel 8, 24 Transfer Complete */
      DMA9_DMA25_IRQn              = 9,                /**< DMA Channel 9, 25 Transfer Complete */
      DMA10_DMA26_IRQn             = 10,               /**< DMA Channel 10, 26 Transfer Complete */
      DMA11_DMA27_IRQn             = 11,               /**< DMA Channel 11, 27 Transfer Complete */
      DMA12_DMA28_IRQn             = 12,               /**< DMA Channel 12, 28 Transfer Complete */
      DMA13_DMA29_IRQn             = 13,               /**< DMA Channel 13, 29 Transfer Complete */
      DMA14_DMA30_IRQn             = 14,               /**< DMA Channel 14, 30 Transfer Complete */
      DMA15_DMA31_IRQn             = 15,               /**< DMA Channel 15, 31 Transfer Complete */
      DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
      MCM_IRQn                     = 17,               /**< Normal Interrupt */
      FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
      Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
      LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
      LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
      WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
      RNG_IRQn                     = 23,               /**< RNG Interrupt */
      I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
      I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
      SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
      SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
      I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
      I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
      Reserved46_IRQn              = 30,               /**< Reserved interrupt 46 */
      UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
      UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
      UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
      UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
      UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
      UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
      UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
      UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
      ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
      CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
      CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
      FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
      FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
      FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
      CMT_IRQn                     = 45,               /**< CMT interrupt */
      RTC_IRQn                     = 46,               /**< RTC interrupt */
      RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
      PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
      PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
      PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
      PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
      PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
      USB0_IRQn                    = 53,               /**< USB0 interrupt */
      USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
      Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
      DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
      MCG_IRQn                     = 57,               /**< MCG Interrupt */
      LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
      PORTA_IRQn                   = 59,               /**< Port A interrupt */
      PORTB_IRQn                   = 60,               /**< Port B interrupt */
      PORTC_IRQn                   = 61,               /**< Port C interrupt */
      PORTD_IRQn                   = 62,               /**< Port D interrupt */
      PORTE_IRQn                   = 63,               /**< Port E interrupt */
      SWI_IRQn                     = 64,               /**< Software interrupt */
      SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
      UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
      UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
      Reserved84_IRQn              = 68,               /**< Reserved interrupt 84 */
      Reserved85_IRQn              = 69,               /**< Reserved interrupt 85 */
      CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
      FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
      DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
      ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
      I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
      CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
      CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
      CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
      CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
      CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
      CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
      SDHC_IRQn                    = 81,               /**< SDHC interrupt */
      ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
      ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
      ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
      ENET_Error_IRQn              = 85,               /**< Ethernet MAC Error and miscelaneous Interrupt */
      LPUART0_IRQn                 = 86,               /**< LPUART0 status/error interrupt */
      TSI0_IRQn                    = 87,               /**< TSI0 interrupt */
      TPM1_IRQn                    = 88,               /**< TPM1 fault, overflow and channels interrupt */
      TPM2_IRQn                    = 89,               /**< TPM2 fault, overflow and channels interrupt */
      USBHSDCD_IRQn                = 90,               /**< USBHSDCD, USBHS Phy Interrupt */
      I2C3_IRQn                    = 91,               /**< I2C3 interrupt */
      CMP3_IRQn                    = 92,               /**< CMP3 interrupt */
      USBHS_IRQn                   = 93,               /**< USB high speed OTG interrupt */
      CAN1_ORed_Message_buffer_IRQn = 94,              /**< CAN1 OR'd message buffers interrupt */
      CAN1_Bus_Off_IRQn            = 95,               /**< CAN1 bus off interrupt */
      CAN1_Error_IRQn              = 96,               /**< CAN1 error interrupt */
      CAN1_Tx_Warning_IRQn         = 97,               /**< CAN1 Tx warning interrupt */
      CAN1_Rx_Warning_IRQn         = 98,               /**< CAN1 Rx warning interrupt */
      CAN1_Wake_Up_IRQn            = 99                /**< CAN1 wake up interrupt */
    } IRQn_Type;	//对应中断矢量分配表(3-3 Interrupt vector assignments)
  3. 系统函数
    优先级分组

    /** \brief  Set Priority Grouping
    
      This function sets the priority grouping field using the required unlock sequence.
      The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
      Only values from 0..7 are used.
      In case of a conflict between priority grouping and available
      priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
    
      \param [in]      PriorityGroup  Priority grouping field
     */
    static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
    {
      uint32_t reg_value;
      uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
    
      reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
      reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
      reg_value  =  (reg_value                                 |
               ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
               (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
      SCB->AIRCR =  reg_value;
    }
    /*------------------------------------------------------------------------------------------------------
    【函    数】GPIO_ExtiInit
    【功    能】GPIO初始化
    【参    数】ptx_n : 要初始化的GPIO, 在common.h中定义
    【返 回 值】无
    【实    例】GPIO_ExtiInit(PTA17, rising_down); //PTA17管脚上升沿触发中断
    【注意事项】注意需要使用NVIC_SetPriority来配置PIT中断优先级   NVIC_EnableIRQ来使能中断 
    【注意事项】
    【注意事项】优先级配置 抢占优先级1  子优先级2   越小优先级越高  抢占优先级可打断别的中断 
    【注意事项】NVIC_SetPriority(PORTA_IRQn,NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1,2));
    【注意事项】NVIC_EnableIRQ(PORTA_IRQn);			         //使能PORTA_IRQn的中断  
    --------------------------------------------------------------------------------------------------------*/
    void GPIO_ExtiInit(PTXn_e ptx_n, exti_cfg cfg)
    {
        uint8_t ptx,ptn;
        
        ptx = PTX(ptx_n);
        ptn = PTn(ptx_n);
        
        /* 使能端口时钟 */
      SIM->SCGC5 |= (SIM_SCGC5_PORTA_MASK << ptx);
    
        //清除中断标志位
        PORTX[ptx]->ISFR = (uint32)1<<ptn; 	//检测中断
        
        /* 配置端口功能 */
        PORT_PCR_REG(PORTX[ptx], ptn) = PORT_PCR_MUX(1) | PORT_PCR_IRQC(cfg & 0x7f ) | PORT_PCR_PE_MASK | ((cfg & 0x80 ) >> 7);
        //对应寄存器(PARTx,PCRn) = GPIO功能|IRQC为下降触发|启用上拉或者下拉电阻|上拉
        //设置端口为输入
        GPIOX[ptx]->PDDR &= ~(uint32)(1<<ptn);	//GPIO方向
        
    }
    /** \brief  Set Interrupt Priority
    
      This function sets the priority for the specified interrupt. The interrupt
      number can be positive to specify an external (device specific)
      interrupt, or negative to specify an internal (core) interrupt.
    
      Note: The priority cannot be set for every core interrupt.
    
      \param [in]      IRQn  Number of the interrupt for set priority
      \param [in]  priority  Priority to set
     */
    static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
    {
      if(IRQn < 0)
      {
        //SCB->SHP[0-11]系统处理优先级寄存器 用于系统异常的中断优先级寄存器
        SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
      } 	//把IRQn对应到SCB->SHP[功能位置] = (根据寄存器宽度 移位相应位数 得到优先级)
      else
      {
        NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);
      }        /* set Priority for device specific Interrupts  */
    }
    /** \brief  Encode Priority
    
      This function encodes the priority for an interrupt with the given priority group,
      preemptive priority value and sub priority value.
      In case of a conflict between priority grouping and available
      priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
    
      The returned priority value can be used for NVIC_SetPriority(...) function
    
      \param [in]     PriorityGroup  Used priority group
      \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
      \param [in]       SubPriority  Sub priority value (starting from 0)
      \return                        Encoded priority for the interrupt
     */
    static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
    {
      uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
      uint32_t PreemptPriorityBits;
      uint32_t SubPriorityBits;
      //K66具有4位优先级宽度 16个中断优先级 (低4位恒为零)
      //即开启了优先级7-3 对应寄存器值为111(7)-011(3),优先级010(2)-000(0)认为是优先级3
      PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
      //确定 分组优先级有几位
      SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
      //确定 子优先级  有几位
      return (
             ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
             ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
           );//基于优先级分组、分组优先级和子优先级生成优先级数值
    }
    static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
    {
      return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
      //返回SCB->AIRCR[10:8]>>8 = AIRCR_PRIGROUP的状态 即读取优先级分组
    }
    static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
    {
      /*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
      NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
      //确定ISER为uint32_t只能放32位,需要构成数组来储存更多,IRQn>>5确定数组编号 IRQn&0x1F确定位置
    }
  4. 功能函数
    /*LLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLLL
    【作  者】LQ-005
    【功能说明】测试按键  
    【软件版本】V1.0
    【最后更新】2017年11月24日 
    【函数名】
    【返回值】无
    【参数值】无
    QQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQQ*/
    void Test_ExtiKEY(void)
    { 
        LED_Init();
        
        /* 内部上拉 下降沿触发中断 中断服务函数在 IRQ_Handler.c */
        GPIO_ExtiInit(PTB20, falling_up);
        GPIO_ExtiInit(PTB21, falling_up);
        GPIO_ExtiInit(PTB22, falling_up);
        
        /* 优先级配置 抢占优先级1  子优先级2   越小优先级越高  抢占优先级可打断别的中断 */
        NVIC_SetPriority(PORTB_IRQn,NVIC_EncodePriority(NVIC_GetPriorityGrouping(),1,2));
        NVIC_EnableIRQ(PORTB_IRQn);			         //使能PORTB_IRQn的中断  
        while (1)
        {  
            //测试按键      
    
            switch(key_exti_flag)  //
            {
                case 1:
                    LED_Reverse(0);
                    break;           
                case 2:      
                    LED_Reverse(1);
                    break;
                case 3:      
                    LED_Reverse(2);
                    break;
                default:
                    LED_Reverse(3);
                    break;
            }
            //延时
            delayms(50);
        }
    }

     

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